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CS5333
24-Bit, 96 kHz Stereo A/D Converter
Features
l 24-bit
Description
The CS5333 is a highly integrated, 24-bit, 96 kHz audio ADC providing stereo analog-to-digital converters using delta-sigma conversion techniques. This device includes line level inputs in a 16-pin TSSOP package. The CS5333 is based on delta-sigma modulation allowing infinite adjustment of the sample rate between 2 kHz and 100 kHz simply by changing the master clock frequency. The CS5333 operates from a +1.8 V to +3.3 V supply.
conversion l Supports 96 kHz sample rates l 98 dB dynamic range at 3 V supply l -88 dBFS THD+N l 1.8 to 3.3 volt supply l 16-Pin TSSOP package l Low power consumption
- 11 mW at 1.8 V
l Internal
high pass filter to remove DC offsets These features are ideal for set-top boxes, A/V receivers, DVD-karaoke players or any system which requires l Linear phase digital anti-alias filter optimal performance in a minimum of space.
ORDERING INFORMATION CS5333-KZ -10 to 70 C CDB5333
II
16-pin TSSOP Evaluation Board
V A V L RS T
+ AINL S/H C omparator DAC S e r i al P o rt LP Filter + Digital Decimation Filter HPF SDATA LRCK SCLK
+ AINR S/H C omparator DAC LP Filter + Digital Decimation Filter HPF
TST
GND
VQ
MCLK
FIL T +
REF_G ND
DIV
DIF
Advance Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2000 (All Rights Reserved)
DEC `00 DS520PP1 1
CS5333
TABLE OF CONTENTS
1. CHARACTERISTICS/SPECIFICATIONS ................................................................................. 4 ANALOG CHARACTERISTICS ................................................................................................ 4 ANALOG CHARACTERISTICS ................................................................................................ 5 POWER AND THERMAL CHARACTERISTICS....................................................................... 6 DIGITAL CHARACTERISTICS ................................................................................................. 7 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 7 RECOMMENDED OPERATING CONDITIONS ....................................................................... 7 SWITCHING CHARACTERISTICS .......................................................................................... 8 2. TYPICAL CONNECTION DIAGRAM .................................................................................... 10 3. PIN DESCRIPTION ............................................................................................................... 11 4. APPLICATIONS ...................................................................................................................... 13 4.1 Grounding and Power Supply Decoupling ....................................................................... 13 4.2 Oversampling Modes ....................................................................................................... 13 4.3 Recommended Power-up Sequence ............................................................................... 13 4.4 Master/Slave Mode .......................................................................................................... 13 5. PARAMETER DEFINITIONS .................................................................................................. 17 6. REFERENCES ........................................................................................................................ 17 7. PACKAGE DIMENSIONS ....................................................................................................... 18
Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website or disk. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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LIST OF FIGURES
Figure 1. SCLK to LRCK and SDATA, Slave Mode ........................................................................ 9 Figure 2. SCLK to LRCK and SDATA, Master Mode ...................................................................... 9 Figure 3. Typical Connection Diagram.......................................................................................... 10 Figure 4. Base-Rate Stopband Rejection...................................................................................... 14 Figure 5. Base-Rate Transition Band............................................................................................ 14 Figure 6. Base-Rate Transition Band (Detail) ............................................................................... 14 Figure 7. Base-Rate Passband Ripple.......................................................................................... 14 Figure 8. High-Rate Stopband Rejection ...................................................................................... 14 Figure 9. High-Rate Transition Band............................................................................................. 14 Figure 10. High-Rate Transition Band (Detail) .............................................................................. 15 Figure 11. High-Rate Passband Ripple......................................................................................... 15 Figure 12. Line Input Test Circuit .................................................................................................. 15 Figure 13. CS5333 - Serial Audio Format 0 .................................................................................. 16 Figure 14. CS5333 - Serial Audio Format 1 .................................................................................. 16
LIST OF TABLES
Table 1. Common Clock Frequencies........................................................................................... 11 Table 2. Digital Interface Format - DIF.......................................................................................... 12
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1. CHARACTERISTICS/SPECIFICATIONS
ANALOG CHARACTERISTICS (TA = 25 C; GND = 0 V Logic "1" = VL = 1.8 V; Logic "0" =
GND = 0 V; MCLK = 12.288 MHz; Fs for Base-rate Mode = 48 kHz, SCLK = 3.072 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for High-Rate Mode = 96 kHz, SCLK = 6.144 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.) Base-rate Mode Parameter Symbol Analog Input Characteristics for VA = 1.8 V Dynamic Range A-weighted unweighted Total Harmonic Distortion + Noise (Note 1) THD+N -1 dB -20 dB -60 dB Analog Input Characteristics for VA = 3.0 V Dynamic Range A-weighted unweighted Total Harmonic Distortion + Noise (Note 1) THD+N -1 dB -20 dB -60 dB Analog Input Characteristics for VA = 1.8 or 3.0 V Interchannel Isolation 1 kHz Interchannel Gain Mismatch Offset Error with High Pass Filter Full Scale Input Voltage Voltage Common Mode Gain Drift Input Resistance Input Capacitance Min TBD TBD TBD TBD Typ 91 88 -88 -68 -28 96 93 -88 -68 -33 Max TBD TBD High-rate Mode Min TBD TBD TBD TBD Typ 94 91 -88 -68 -31 98 95 -85 -65 -35 Max TBD TBD Unit dB dB dB dB dB dB dB dB dB dB
90 0.1 0 TBD VA/3.6 TBD VA/2 100 10 15
90 dB 0.1 dB 0 LSB TBD VA/3.6 TBD Vrms VA/2 V 100 - ppm/C 10 k 15 pF
Notes: 1. Referenced to typical full-scale differential input voltage.
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ANALOG CHARACTERISTICS (Continued)
Base-rate Mode Parameter Symbol Min A/D Decimation Filter Characteristics (Note 2) Passband (Note 3) 0 Passband Ripple -0.08 Stopband (Note 3) 27.5 Stopband Attenuation (Note 4) -60.3 Group Delay (Fs = Output Sample Rate) (Note 5) tgd Group Delay Variation vs. Frequency tgd (Note 3) (Note 3) (Note 2) Typ 10/Fs 3.7 24.2 10 Max High-rate Mode Min Typ 2.7/Fs 3.7 24.2 10 Max 47.5 0 0.007 Unit kHz dB kHz dB s s
23.5 0 +0.17 -0.09 64.1 -48.4 0.03 0.17 -
High Pass Filter Characteristics Frequency Response -3 dB -0.1 dB Phase Deviation @ 20 Hz Passband Ripple
Hz Hz Degree 0.09 dB
Notes: 2. Filter response is guaranteed by design. 3. Filter characteristics scale with output sample rate. For output sample rates, Fs, other than 48 kHz, the 0.01 dB passband edge is 0.4535x Fs and the stopband edge is 0.625x Fs. 4. The analog modulator samples the input at 6.144 MHz for an Fs equal to 48 kHz. There is no rejection of input signals which are multiples of the sampling frequency (n x 6.144 MHz 21.8 kHz where n = 0,1,2,3...). 5. Group delay for Fs = 48 kHz, tgd = 15/48 kHz = 312 s.
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POWER AND THERMAL CHARACTERISTICS
Base-rate Mode Parameters Symbol Min Typ 6.0 150 100 0 9 260 250 0 11 28 75 60 40 Max TBD TBD High-Rate Mode Min Typ 7.6 300 250 0 11.5 520 500 0 14.5 36 75 60 40 Max TBD TBD Units mA A A A mA A A A mW mW C/Watt dB dB
Power Supplies Power Supply CurrentVA=1.8 V IA Normal Operation VL=1.8 V ID_IO Power Supply CurrentVA=1.8 V IA Power Down Mode (Note 7) VL=1.8 V ID_IO Power Supply CurrentVA=3.0 V IA Normal Operation VL=3.0 V ID_IO Power Supply CurrentVA=3.0 V IA Power Down Mode VL=3.0 V ID_IO Total Power DissipationAll Supplies=1.8 V Normal Operation All Supplies=3.0 V Package Thermal Resistance JA Power Supply Rejection Ratio (1 kHz) PSRR (Note 6) (60 Hz)
Notes: 6.
Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 3.
7. Power Down Mode is defined as reset active with MCLK being applied. To lower power consumption further, remove MCLK.
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DIGITAL CHARACTERISTICS (TA = 25 C; VL =
Parameters High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Leakage Current Input Capacitance 1.7 V - 3.6 V; GND = 0 V) Min 0.7*VL 0.7*VL Typ 8 Max 0.3*VL 0.3*VL 10 Units V V V V A pF
Symbol VIH VIL VOH VOL Iin
ABSOLUTE MAXIMUM RATINGS (GND = 0 V; all voltages with respect to ground.)
Parameters DC Power Supplies: Positive Analog Digital I/O Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Operating Temperature (power applied) Storage Temperature Symbol VA VL Iin VIND TA Tstg Min -0.3 -0.3 -0.3 -55 -65 Max 4.0 4.0 10 VL+0.4 125 150 Units V V mA V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (GND = 0 V; all voltages with respect to ground.)
Parameters Ambient Temperature DC Power Supplies: Positive Analog Digital I/O Symbol TA VA VL Min -10 1.7 1.7 Typ Max 70 3.6 3.6 Units C V V
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SWITCHING CHARACTERISTICS (TA = -10 to 70 C; VL = 1.7 V - 3.6 V; Inputs: Logic 0 = GND,
Logic 1 = VL, CL = 20 pF) Parameters Input Sample Rate MCLK Pulse Width High MCLK Pulse Width Low MCLK Pulse Width High MCLK Pulse Width Low MCLK Pulse Width High MCLK Pulse Width Low MCLK Pulse Width High MCLK Pulse Width Low MCLK Pulse Width High MCLK Pulse Width Low Base Rate Mode High Rate Mode MCLK/LRCK = 1024 MCLK/LRCK = 1024 MCLK/LRCK = 768 MCLK/LRCK = 768 MCLK/LRCK = 512 MCLK/LRCK = 512 MCLK / LRCK = 384 or 192 MCLK / LRCK = 384 or 192 MCLK / LRCK = 256 or 128 MCLK / LRCK = 256 or 128 tslrd tsdo Symbol Fs Fs Min 2 50 8 8 10 10 15 15 21 21 31 31 -20 0 40 tsclkl tsclkh Base Rate Mode High Rate Mode SCLK Falling to LRCK Edge SCLK Falling to SDATA Valid Base Rate Mode High Rate Mode tsclkw tsclkw tslrd tdss tdss 20 20
1 --------------------( 128 )Fs 1 -----------------( 64 )Fs
Typ 50 50 -
Max 50 100 20 20 60 20
1 (512)Fs 1 (256)Fs
Units kHz kHz ns ns ns ns ns ns ns ns ns ns ns ns % % ns ns ns ns ns ns ns
Master Mode SCLK Falling to LRCK Edge SCLK Falling to SDATA Valid SCLK Duty Cycle Slave Mode LRCK Duty Cycle SCLK Pulse Width Low SCLK Pulse Width High SCLK Period
-20 -
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t sclkh SCLK t sclkl LRCK t dss SDATA MSB t slrd
t sclkw
Figure 1. SCLK to LRCK and SDATA, Slave Mode
SCLK t slrd LRCK t sdo SDATA MSB MSB-1
Figure 2. SCLK to LRCK and SDATA, Master Mode
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2. TYPICAL CONNECTION DIAGRAM
1.8 to 3.3 V Supply
+ 1.0 F
0.1 F 5 VA FILT+
11 1.0 F +
1.8 to 3.3 V Supply + 1.0 F
1 VL 0.1 F
REF_GND 12
150
0.47 F * **
14
VQ 15 AINL
+ 1.0 F
0.01 F * 13 AINR
CS5333
RST DIF DIV 16 9 8 Mode Configuration
150
0.47 F * **
0.01 F *
* All capacitors located on the analog input lines should be of the type COG or equivalent. **Optional if analog input circuit is biased within 5% of CS5333 nominal bias voltage
MCLK LRCK SCLK SDATA GND 6 TST 10
2 7 3 4 Digital Audio Source
47k
Connect to: * VL for Master Mode * GND for Slave Mode
Figure 3. Typical Connection Diagram
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3. PIN DESCRIPTION
Interface Power Master Clock Serial Clock Serial Data Output Analog Power Ground Left Right Clock MCLK Divide VL MCLK SCLK SDATA VA GND LRCK DIV 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 RST Reset VQ Quiescent Voltage AINL Left Channel Analog Input AINR Right Channel Analog Input REF_GND Reference Ground FILT+ Positive Voltage Reference TST Test Input DIF Digital Interface Format
Interface Power Master Clock
1 2
VL (Input) - Digital interface power supply. Typically 1.8 to 3.3 VDC. MCLK (Input) - The master clock frequency must be either 256x, 384x, 512x, 768x or 1024x the input sample rate in Base Rate Mode (BRM) and 128x, 192x, 256x, 384x the input sample rate in High Rate Mode (HRM). Table 1 illustrates several standard audio sample rates and the required master clock frequencies. SCLK (Input/Output) - Clocks the individual bits of the serial data out of the SDOUT pin. The required relationship between the Left/Right clock, serial clock and serial data is defined by the DIF pin. SDATA (Output) - This pin serves two functions. First: two's complement MSB-first serial data is output on this pin. The data is clocked out of SDOUT via the serial clock and the channel is determined by the Left/Right clock. The required relationship between the Left/Right clock, serial clock and serial data is defined by the DIF pin. Second: Master/Slave mode selection is determined, at startup, by a 47 kOhm pullup/pulldown on this line. A pullup to VL selects Master mode and a pulldown to GND selects Slave mode. VA (Input) - Analog power supply. Typically 1.8 to 3.3 VDC. GND (Input) - Ground Reference.
Serial Clock
3
Serial Audio Data Out (M/S select)
4
Analog Power Ground
5 6
MCLK (MHz) Sample Rate (kHz) 32 44.1 48 64 88.2 96 HRM 128x 4.0960 5.6448 6.1440 8.1920 11.2896 12.2880 192x 6.1440 8.4672 9.2160 12.2880 16.9344 18.4320 256x* 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 384x* 12.2880 16.9344 18.4320 24.5760 33.8688 36.8640 256x 8.1920 11.2896 12.2880 384x 12.2880 16.9344 18.4320 BRM 512x 16.3840 22.5792 24.5760 768x* 24.5760 32.7680 36.8640 1024x* 32.7680 45.1584 49.1520 -
* DIV= Hi
Table 1. Common Clock Frequencies DS520PP1 11
CS5333
Left/Right Clock 7 LRCK (Input/Output) - The Left/Right clock determines which channel is currently being output on the serial audio data line SDOUT. The frequency of the Left/Right clock must be at the input sample rate. The required relationship between the Left/Right clock, serial clock and serial data is defined by the DIF pin. DIV (Input) - This pin serves different functions in Master and Slave modes. In Master mode: When high, the chip will enter High Rate Mode; When this pin is low, the chip will enter Base Rate Mode. In Slave mode: When high, MCLK is divided internally by 2; When low, MCLK is not changed. DIF (Input) - The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format. DIF 0 1 DESCRIPTION I2S, up to 24-bit data Left Justified, up to 24-bit data
MCLK Divide Enable
8
Digital Interface Format
9
Table 2. Digital Interface Format - DIF
Test Input Positive Voltage Reference 10 11 TST (Input) - Must be connected directly to ground. FILT+ (Output) - Positive reference for internal sampling circuits. An external capacitor is required from FILT+ to ground, as shown in Figure 3. The recommended value will typically provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 60 Hz. FILT+ is not intended to supply external current. FILT+ has a typical source impedance of 250 k and any current drawn from this pin will alter device performance. REF_GND (Input) - Ground reference for the internal sampling circuits. Must be connected to ground. AINR, AINL (Input) - The full scale analog input level is specified in the Analog Characteristics specification table. VQ (Output) - Filter connection for internal A/D converter quiescent reference voltage. A capacitor must be connected from VQ to ground. VQ is not intended to supply external current. VQ has a typical source impedance of 250 k and any current drawn from this pin will alter device performance. RST (Input) - When low the device enters a low power mode and the part is in reset. When high, the part returns to normal operation within 1024 LRCK cycles.
Reference Ground Analog Inputs Quiescent Voltage
12 13,14 15
Reset
16
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4. APPLICATIONS 4.1 Grounding and Power Supply Decoupling 4.4
the power-up sequence. This power-up sequence takes approximately 1024 LRCK cycles to complete.
As with any high resolution converter, the CS5333 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 3 show the recommended power arrangement with VA and VL connected to clean supplies. Decoupling capacitors should be located as close to the device package as possible.
Master/Slave Mode
4.2
Oversampling Modes
In Master, Base Rate Mode (Pull-up on SDATA, DIV=0), the CS5333 requires a 256x MCLK and provide a 64x SCLK. In Master, High Rate Mode (Pull-up on SDATA, DIV=1), the CS5333 requires a 128x MCLK and provide a 64x SCLK. The various clocking ratios required in Slave Mode (Pulldown on SDATA) are listed under the description of MCLK, on page 11.
The CS5333 operates in one of two oversampling modes. Base Rate Mode supports input sample rates up to 50 kHz while High Rate Mode supports input sample rates up to 100 kHz. See Table 1 for more details.
4.3
Recommended Power-up Sequence
1) Hold RST low until the power supply, master, and left/right clocks are stable. In this state, VQ will remain low. 2) Bring RST high. The device will remain in a low power state with VQ low and will initiate
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0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (normalized to Fs)
0 -10 -20 Amplitude dB -30 -40 -50 -60 -70 -80 -90 -100 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6
Amplitude dB
Frequency (normalized to Fs)
Figure 4. Base-Rate Stopband Rejection
0 -1 -2 Amplitude dB -4 -5 -6 -7 -8 -9 -10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55
Amplitude dB 0.3 0.25 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 0
Figure 5. Base-Rate Transition Band
-3
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 6. Base-Rate Transition Band (Detail)
Figure 7. Base-Rate Passband Ripple
0 -10 -20 Amplitude dB -40 -50 -60 -70 -80 -90 -100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (normalized to Fs) -30
0 -10 -20 Amplitude dB -30 -40 -50 -60 -70 -80 -90 -100 0.4 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67
Frequency (normalized to Fs)
Figure 8. High-Rate Stopband Rejection
Figure 9. High-Rate Transition Band
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0 -1 -2 Amplitude dB -3 -4 -5 -6 -7 -8 -9 -10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55
Amplitude dB
0.3 0.25 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 10. High-Rate Transition Band (Detail)
Figure 11. High-Rate Passband Ripple
150
0.47 F AINx 0.01 F
GND
Figure 12. Line Input Test Circuit
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CS5333
LRCK SCLK
Left Channel
Right Channel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
I2S, up to 24-Bit Data. Data Valid on Rising Edge of SCLK Figure 13. CS5333 - Serial Audio Format 0
LRCK SCLK
Left Channel
Right Channel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Left Justified, up to 24-Bit Data. Data Valid on Rising Edge of SCLK.
Figure 14. CS5333 - Serial Audio Format 1
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5. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C.
6. REFERENCES
1. "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2. CDB5333 Evaluation Board Datasheet.
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7. PACKAGE DIMENSIONS
16L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11 A2 A1
L
E
A
e b2 SIDE VIEW END VIEW SEATING PLANE
123
TOP VIEW
DIM A A1 A2 b D E E1 e L
MIN -0.002 0.03346 0.00748 0.193 0.248 0.169 -0.020 0
INCHES NOM -0.004 0.0354 0.0096 0.1969 0.2519 0.1732 0.026 BSC 0.024 4
MAX 0.043 0.006 0.037 0.012 0.201 0.256 0.177 -0.028 8
MIN -0.05 0.85 0.19 4.90 6.30 4.30 -0.50 0
MILLIMETERS NOM --0.90 0.245 5.00 6.40 4.40 0.065 BSC 0.60 4
NOTE MAX 1.10 0.15 0.95 0.30 5.10 6.50 4.50 -0.70 8
2,3 1 1
JEDEC #: MO-153 Controlling Dimension is Millimeters Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.
2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips
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* Notes *

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